Identification and Test Generation for Primitive Faults

We propose a new method to identify and test primitive faults in combinational circuits described as multi-level or two-level netlists. A primitive fault is a multiple path delay fault for which none of the single paths contained in the fault is robustly or non-robustly testable while the presence of the fault can degrade the circuit performance. Identiication and testing of primitive faults is important for at least two reasons: (1) a large percentage of paths in production circuits remain untestable under the single-path delay fault model, (2) distributed manufacturing defects usually adversely aaect more than one path and these defects can be detected only by analyzing multiple aaected paths. The single-path delay faults contained in a primitive fault have to merge at some gate(s). Our methodology for identifying primitive faults can quickly (1) rule out a large number of gates as possible merging points for primitive faults, and (2) prune the combination of paths that can never belong to any primitive fault. Our identiication procedure also nds a test for the fault. We present a complete algorithm for identifying and testing double path delay faults. This procedure can be extended to identify primitive faults consisting of three or more paths. Experimental results on several multi-level combina-tional benchmark circuits are included to demonstrate the usefulness of our technique.